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ASIC Physical Design Engineer

  • Responsible for RTL2GDS implementation of multi-hierarchy designs
  • Work closely with RTL design team to understand the design architecture and drive design physical planning aspects
  • As a member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work
Qualifications & Competencies
  • 7+ years of HW engineer work experience with a broad mix of technologies including all aspects of ASIC Physical implementation: Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration, Hierarchical design implementation approach, Timing closure, Physical convergence, Power Integrity Analysis
  • Experienced with large designs (>100M gates) utilizing state of the art sub 16nm technologies
  • Fluent English
Benefits Package
  • Medical insurance (package for the whole family)
  • Life insurance for an employee
  • Welcome bonus
  • Stock options + discount for stock options

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